By Liqiang He, Cha Narisu (auth.), Yong Dou, Ralf Gruber, Josef M. Joller (eds.)
This booklet constitutes the refereed lawsuits of the eighth overseas Workshop on complicated Parallel Processing applied sciences, APPT 2009, held in Rapperswil, Switzerland, in August 2009.
The 36 revised complete papers provided have been conscientiously reviewed and chosen from seventy six submissions. All present facets in parallel and dispensed computing are addressed starting from and software program concerns to algorithmic facets and complicated functions. The papers are prepared in topical sections on structure, graphical processing unit, grid, grid scheduling, cellular software, parallel program, parallel libraries and performance.
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Additional info for Advanced Parallel Processing Technologies: 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009 Proceedings
The lightweight shared cache improves the performance of CMP by 6% on average. 6 Storage Overhead The lightweight shared cache will consume some on-chip resource, while the memory space of directory in L2 cache is saved. 18%. The detailed storage overhead can be seen in Table 4. As the number of cores increases, the saved directory storage from L2 cache will increase signiﬁcantly, while the storage overhead of the proposed scheme will increase far slower. So, the proposed lightweight shared cache design can provide much better scalability than the conventional shared L2 cache design.
Since shared data access and directory maintenance are correlated with network communication, the proposed scheme embeds SDC and VDC into the network interface of each router to decrease L1 cache miss latency further. Full-system simulations of 16-core CMP show that the lightweight shared cache scheme provides the robust performance: it decreases L1 miss latency by 20% on average and reduces oﬀ-chip memory requests by 13% on average. 18% storage overhead. 30 J. Wang et al. The rest of the paper is organized as follows: Section 2 presents a review of the related work.
From previous experiment, the number of data blocks recently cached by L1 caches in L2 cache does not exceed 41% of the capacity of L1 caches on average. According to temporal locality, we place these data blocks in the proposed lightweight shared cache in the home node. Most of L1 miss requests sent to this home node will be satisﬁed in the lightweight shared cache and need not travel to L2 cache bank to access data blocks. The lightweight shared cache should have desirable space to contain blocks recently cached by L1 caches.
Advanced Parallel Processing Technologies: 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009 Proceedings by Liqiang He, Cha Narisu (auth.), Yong Dou, Ralf Gruber, Josef M. Joller (eds.)