By Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Advanced attempt tools for SRAMs: potent recommendations for Dynamic Fault Detection in Nanoscaled Technologies
Modern electronics will depend on nanoscaled applied sciences that current new demanding situations by way of checking out and analysis. thoughts are quite at risk of defects considering the fact that they take advantage of the know-how limits to get the top density. This booklet is a useful advisor to the trying out and analysis of the newest new release of SRAM, some of the most favourite kind of thoughts. Classical tools for trying out reminiscence are designed to address the so-called "static faults", yet those try strategies are usually not adequate for faults which are rising within the most up-to-date Very Deep Sub-Micron (VDSM) applied sciences. those new faults, known as "dynamic faults", will not be coated by way of classical algorithms and require the committed attempt and analysis recommendations awarded during this book.
- First publication to give entire, cutting-edge assurance of dynamic fault checking out for SRAM memories;
- Presents content material utilizing a "bottom-up" method, from the research of factors of malfunctions as much as the iteration of clever attempt techniques;
- Includes case reviews protecting all reminiscence parts (core-cells, deal with decoders, write drivers, experience amplifiers, etc.);
- Proposes an exhaustive research of resistive-open defects in every one reminiscence part and the ensuing dynamic fault modeling.
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Additional info for Advanced Test Methods for SRAMs: Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies
It requires three main inputs: (i) the Fault List, (ii) the applied March test, and (iii) the Memory Model. The results of the fault simulation are the Coverage Report and the Fault Dictionary. Fig. 7 Memory fault simulator architecture Fault List March Test Memory Model Memory-Fault Simulator Coverage Report Fault Dictionary The memory fault simulation is based on the serial fault simulation paradigm. The fault F is injected into the memory and the March test is applied. The values of the read operations of the simulated March tests are used to monitor the memory behavior in the presence of F.
4). The following four columns correspond to the values of the parameters that maximize the fault detection. The last column gives the fault models corresponding to each defect. 2 Summary of worst-case PVT corners for the defects of Fig. 6 –40 – 125 125 –40 125 ∼25k ∼8k ∼3k ∼130k/∼130k/80 M 100k/140 k ∼2 M TF RDF/DRDF/(dDRF) RDF/DRDF/(dDRF) dRDF/dDRF/DRF IRF/TF TF The experiments demonstrate that the detection sequences 1w0r0 and 0w1r1 are the most effective for sensitization of the faults linked to the core-cell resistive-open defects (Borri et al.
A w0 operation immediately followed by M r0 operations causes the swap of the core-cell, and a logic ‘1’ is observed at the memory output. M is the number of read operations performed after the write operation (M ≥ 1). The second group of FPs corresponds to the symmetric defect and uses essentially w1 and r1 operations: – FP3: <1w1 r1 M /0/0> A logic ‘1’ is initially stored in the cell. A w1 operation immediately followed by M r1 operations causes the swap of the core-cell content, and a logic ‘0’ is observed at the memory output.
Advanced Test Methods for SRAMs: Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies by Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel